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ADF4351: Optimized Frac-N Settings

Question asked by marshall.beck on Jan 2, 2018
Latest reply on Jan 8, 2018 by Brigid.Duggan



I have one ADF4351 in my system being swept from 2.4G to 4.4G. Right now I am looking to optimize the loop settings of the PLL to minimize the high-order IBS power.


The board I have is a copy of the ADI eval. board schematic. The final system will use the same configuration, as well, use the same 25M crystal for the ADF4351.


I am looking to follow a similar procedure outlined in Robert Brennan's article about ADIsimFrequencyPlanner to generate a lookup table for the sweep range, and then implement that in the processor's firmware. 


Would this be the appropriate design step to take in minimizing the effects of these spurs? Are there any other hooks in the part to get better spur performance for a fixed reference frequency?


I have attached my ADI SFP settings below for channel spacing being set to 10kHz. I would be interested in knowing if the settings are correct for my setup. Is there any documentation for using the ADF4351 w/ this software?