While using Frequency hopping, with fastlock profiling the lock time of PLL in between the hop is reduced to 20us, but if I'm going to hop more than 100MHz, then what are the extra calibrations that are needs to be taken care of?
In reference manual, it is mentioned that Tx quadrature calibration will take 94464 ClkRF cycles(worst case) which will be 10ms if my clock rate at the output of Rx FIR filter is 3.072MHz. So, if I'm going to hop more than 100MHz than will i need to provide 20us + 10ms as the interval between hops?
What else are the calibrations required if hopping is more than 100MHz?
What will be the average time required for DC calibration and quadrature calibration and on what factors these timings will depends on?