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ADF4351 - Fast Log Mode

Question asked by pohchuan.leng on Dec 27, 2017

I'm testing with ADF4351 now and I meet a problem with fast lock mode of this chip.

I config following document guide:

- In hardware I make SW pin connect with extend loop filter following guilde in (p23 of the datasheet) with circuit I attached in mail with name "FastLockLoopFilter.png"

- Also, in software I config with following fast lock example (p22 of the datasheet)

+ Load Register 3 by setting Bits[DB16:DB15] to 01.

+ Set bit DB23 of Register 3 =1 (band select clock mode = high)

+ Loade by the 12-bit clock divider value (Bits[DB14:DB3] in Register 3) 

 

But I can't see any time change. The lock time still  approximately 88us. Can you help me to see figure I attached in mail with name " normalLockTime.jpg"

 

I only get  lock time lower than 30us by setting "8 bit band select clock  divided value" Bít[DB19:DB12] of Register 4 from 200 to 50  equivalent " band clock select" from 125khz to 500 khz. You can check figure attached in mail with name "fastlockmode.jpg".

Now I'm still unclear the concept " Band clock select" in "Analog Device ADF435X software", you can see in picture with name "BandSelectClock.jpg". It only value when I change I can get lock time change. Can you help me to clear this concept?

And one morething, when I get lock time lower 30us, I try to change DB23 of Register 3 or bit [DB16:DB15} in Register 4 but the locktime  like not change. So I don't know if I have configurated correct time fast lock mode ?

 

thank you.

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