I designed a PLL circuit using ADF4157. The VCO module of the PLL is a board VCO I designed myself. The output frequency of the VCO is about 1.250GHz. Kv is 6MHz/V ,and it can work properly. I use 51MCU(STC89LE52RC) to configure of the register of ADF4157. All power supply parts are used for external power supply and filter with capacitance. The part of loop filter is calculated using ADIsimPLL. The output frequency is set to 1.250GHz. reference frequency is 12MHz, loop band is 25kHz, Phase Margin is 45 deg. The voltage of AVdd and DVdd is 3V. Vp is 5V.
Icp is 5mA. And the pin of MUXOUT is suspended in midair. Since I design this PLL circuit as a sensor, I didn’t use the function of the fast lock, and I just hope the PLL circuit can lock. But the PLL circuit was always unclocked when I tested. Every time I powed up the PLL and configured the register , The output voltage of the loop filter jumped to 5V(Vp) ,resulting unclocked. I tried to change the bandwidth of the loop and the charge pump current, I also attempted to turn on the constant negative bleed current , But the result is the same. I want to know why this happens. I never understood why the output voltage of the low pass filter is always the peak voltage (Vp). The welding of the circuit board should be correct, since I checked many times and welded a lot of boards. Attachments are my schematic and c procedures.
The register is configured as follows:
I am looking forward to your reply,thanks