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ADV7123 analog delays

Question asked by Panos on Dec 25, 2017
Latest reply on Jan 25, 2018 by Panos

I have a few questions about the ADV7123 and its analog delays:


a.  According to the datasheet, the analog output becomes valid 8ns (t6+t7/2 = 7.5+1/2ns @3V3) after the corresponding data input is clocked in. Therefore, when the IC is used at max speed (330MHz or 3ns clock), this delay corresponds to more than 2.5 clock cycles.

   (1)  Is the IC pipelined accordingly?

   (2)  If so, why does the datasheet specify that the pipeline delay (tPD) is only 1 clock cycle?

   (3)  What is the propagation delay of the /Blank and /Sync inputs?

   (4)  Do they also need to be manually delayed by 2.5 clock cycles?

   (5)  Otherwise, is this delay embedded in their logic and therefore they need to be in sync with the data inputs ?


b.  According to the datasheet, the analog output becomes stable (<2% deviation from final value) 15ns (t8) after its appearance. However, with a 3ns clock cycle, the analog output is actually used only at the first 3ns of its appearance. What is the max deviation during this time?