Here is some ADF7023 issues . please check if they should be added in errata .
1) Manchester coding and decoding in ADF7023 is implemented complementary . You can encode some bytes according to manchester rule (described in datasheet or Wiki) and send it via Eval kit to another ADF7023 (receiver) . and enable manchester decoding on receiver side . you will see the bytes decoded are complemented .
When you use manchester encode & decode on both sides , both of them complement bytes and you will not sense the problem . this issue appeared when I was transmitting manchester encoded packet by another transceiver (CC1101 from TI) and receiving them via ADF7023 .
2) Immediately after CMD_HW_RESET, ADF7023 goes to sleep and consumes current less than uA . but 50ms to 100 ms later, ADF7023 will consume about 2mA for a duration of less than 10 ms and current goes low again . I saw this behavior via Ampere meter that was plotting current consumption on PC .
So I don't know if ADF7023 is doing some calibration process or any other task after going to HW_RESET state. But if I can disable this wake up like behavior by any change in register setting, average current consumption of my circuit will be reduced . because I should force ADF7023 in sleep frequently.
3) If you issue CMD_HW_RESET , ADF7023 will consume about 0.5 uA more than current specified in sheet . but if you set BBRAM_Retention_Enable bit before issuing CMD_HW_RESET , the current consumption will be reduced . I don't know why . because HW_RESET state should be independent of RAM retention bit status .
4) Matching circuit that is implemented on Daugther card has 2 LC components more than diagram specified in reference design . please let me know if the difference affects performanc . Can I have updated reference designe with detailed BOM ?
Thanks in advance for you attention