I'm seeing a consistent 180 degree phase difference ( across power cycles ) between CH A and CH B (complex) samples despite (trying) to operate the AD9680 in SUBCLASS 1 mode using an external SYSREF clock.
Initially the external SYSREF clock in off upon board power up.
I'm configuring the AD9680 in N-shot mode ( reg 0x120 = 0x04 and reg 0x121 = 0x0f ).
Both DDC 0 and 1 are enabled, complex outputs.
Chip decimation rate is 8
I am using frequency translation but am taking the default phase adjustment word PAW=0x00.
I reset the DDC_SYNC_CONTROL register (0x300) by writing 0x13 then 10 ms later 0x3 to request N-shot mode after programming the FTW registers 0x314,0x315 and 0x334,0x335.
The SYSREF clock is set to be commensurate with the LMFC period at 3.90625 MHz; but in N-shot mode that shouldn't matter. The SYSREF is clock signal power at the board sma measures 14dBm.
The board is controlled by a Xilinx KCU105. After the fpga boots and prints its boiler plate, I trigger the siggen to produce the SYSREF clock.
Unfortunately, usually, querying the 0x120 register results in 0x00 prior to enabling the SYSREF clock- as if it isn't accepting the register setting? Although, I have (once) read the register 0x120 as 0x04 and 0x121 as 0x0f. In this specific case, enabling SYSREF and then rereading the registers showed 0x00 and 0x00 for both- kinda indicating the AD9680 took the SYSREF signal. But even in this one instance, the data aquired still had the 180 degree phase difference between Channel A and B.
Is there an order or dependancy between the relevant SYSREF registers? What does the "flag" bit indicate in register 0x120, i.e. what does "flag held in reset" indicate? Should that bit be set ?
In other answers, the claim is made that the SYSREF edge should cause the PAW to reload for all converters. I'm missing something.