As I was debugging my board power consumption in Deep Sleep Mode. I noticed that by putting the device in reset (pulling the RESET_L low) there were no significant current savings (<1mA) but removing the IC altogether from the board (de-soldering) I saw a 28mA current savings.
According to the datasheet, the total power down current draw should be 25uA.
- Are there differences between power down and reset? The version I'm using does not have a power-down option.
- What should be the expected current draw in reset ?
I verified that in DSM mode (our processor is put in lowest power state) the ADV7180 clock source is gated (crystal oscillator X3 on the schematic is off.)
Also, all the voltage rails to the ADV7180 are always present, even in DSM mode
Note that the measurements are done at the battery input. I have not been able to measure the current to the IC itself because of the way it is designed, unfortunately (no in-line resistors...)
- What could you attribute the current savings in the absence of the IC while putting in reset does not provide any improvement at all.
Your help with these questions is greatly appreciated.