I am using AD9680 in my design with FMCADC4 board. I am trying to modify the FMCADC4 reference design for Xilinx ZC706 board to my configuration.
I am using 1 ADC on the board. The 2 channels of the ADC is used with 2 DDC blocks and decimation ratio of 8. I have in total 4 virtual converters. I am using the 2 lanes with 5 GBS per line rate.
I have modified the axi_ad9680_xcvr , util_fmcadc4_xcvr and axi_ad9680_jesd cores for 2 lane configuration.
This results in a 64 bit AXI streaming data output from JESD core to the axi_ad9680_core.
The axi_ad9680 is designed for the default full bandwidth configuration, 2 channels and 128 bit data input. It has 2 channels. How can I modify this core to interface to interface the 64-bit bus of the JESD core. Can any one give me a guide line on this.