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AD9680 minimum sample rate and jesd204 Lane line rate support

Question asked by p.avinash@mobiveil.co.in on Dec 18, 2017
Latest reply on Dec 19, 2017 by UmeshJ

I have some queries related to ad9680 ADC

1. 500 MSPS mention in data sheet is per ADC channel or including both channel.

2. Does this chip support following  design requirement 

    250MHz sampling clock, 12 bit ADC resolution, 2 ADC channel per chip, no decimation

3. As per AD9680 datasheet JESD204B support lane line rate 3125mbps - 12.5gbps. the design requirement with above specification is 2.5gbps. does this configuration supported by adc

 

Lane line rate=(M X N' X (10/8) X (FOUT/Decimation Ratio)) / L

                      = (2 X 16 X (10/8) X (250/1)) /4

                      = 2500 X 10^6

                      = 2.5 Gbps

M=2

N'=16

Fout = 250MHz

Decimation Ration=1

L=4 

 

Thanks

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