Hi, we're bringing up the JESD 204B interface with the baseband FPGA on a custom board. The design approach is via an FMC connector and to begin with, we are using a AD9371 evaluation board to eliminate any hardware dependencies. We have the following issue:
Problem: The ADC path framer initialization does not go through. The rx framer status reflects value of 'D 32 which indicates that the CGS stage is not past. The deframer seems to go through fine without issues.
Rx Framer: LaneRate 6144, L = 2, k = 32, M = 4, F = 4
Tx Deframer: LaneRate 6144, L = 4, k = 32, M = 4, F = 2
Orx Framer: LaneRate 6144, L = 2, k = 32, M = 2, F = 2
Scrambling enabled in all cases.
Observations/ test cases:
The sync issued from AD9528, on-chip sysref generation modes are tried for 4,6 and 8 pulses also in N-shot mode and also the continuous mode. This does not help change the status.
Appreciate pointers towards fixing this, please.