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AD9361 datasheet clarification

Question asked by dhgeon on Dec 13, 2017
Latest reply on Jan 4, 2018 by dhgeon

The AD9361 datasheet specifies the data/clock delay parameters t_STX, t_HTX, t_DDRX, and t_DDDV, all of which are specified without test conditions, implying that these values are absolute for all possible AD9361 configurations. The Digital Interface Timing wiki (Digital Interface Timing Verification [Analog Devices Wiki] ) states that "When enabling the FIR filter blocks inside the AD9361, tests have been shown that the data/clock delay slightly shifts." I just wanted to confirm that these 4 parameter min/max values can be relied upon regardless of whether of not the FIR is enabled.

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