I'm using an ADAU1452 eval board and connect a audioboard with TDM16 to the SDATA_IN2.
LRCLK (48K) -> LRCLK_IN2
BCLK (12.5Mhz) -> BCLK_IN2
DATAOUT(8 channel) -> DATA_IN2
The ADAU1452 can't lock. What I'm doing wrong ?
Well, there are a couple of things I see that may be issues.
First is that you say it is TDM 16 but the BCLK frequency is for TDM8 and all you mention is 8 channels so I will assume you meant to say TDM8.
So if the sending board is using TDM16 then you would probably still receive the first 8 channels so that is probably not the problem. The problem may be in how you are interconnecting the two boards. When using flying connections between two boards it can be difficult. TDM16 is very difficult and TDM 8 is only a little better. So detail how you are doing these connections and some pictures would be very helpful.
The ASRC setup looks good for the first ASRC. You will have to set up ASRC 1,2 and 3 as well to get 8 channels.
Can you take a scope plot of the signals being sent over? Taking them on the eval board side of the transmission would be best. Look at my post about taking screenshots for advise on how to take them: https://ez.analog.com/thread/87319-how-to-take-meaningful-screenshots-of-i2s-audio-signals
So I would like to see the signal that you are trying to receive so I can tell the format of the signal. That will dictate some of these other settings on the serial input port.
So my first hunch is that the signal integrity is so bad that the ASRC cannot lock to it or the serial clock input pin circuits cannot properly decode the levels.
Feel free to also post your project file.
It is now working.
Please, can you explain me why to use CLK domain 2 .
Each Serial Input port has their own LRCLK and BCLK pins. So there are pins for serial port 0 ,1, 2, and 3. The normal assumption is that each data line will have its own clock associated with it. So clocks connected to serial port 2 will clock in SDATA 2.
Now they do appear on a multiplexer. It is possible to use any of these serial input port clocks to clock in data coming into another port. This is handy when they all are coming from the same device. For instance, if you have a part that has four I2S outputs you can run all four SDATA pins and only run one of the LRCLK and BCLK signals up to one of the ports. Let's say you run it to the :LRCLK and BCLK pins for serial port 0. Then you simply set all the ports to use clock domain 0 and you saved running six signals on your PCB.
If you are using the ASRC, then you select what data you are sending to the ASRC but you cannot select the clocks in a register. It will use the clocks for the serial data port you choose. So if you choose to get data from serial input port 3 then it will use the clock pins for serial data 3 to clock the ASRC and determine the incoming sampling rate.
There is one small bug that is actually not a big problem. If you set a serial port to be a master, let's say port 0, then you cannot use clock domain 0 to clock the other ports. There is no signal being sent. This is because the assumption is that if you were using a port as a master then another port simply has to be set to master and that would put them on the same clock domain.
Retrieving data ...