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DAQ2 FPGA reference clock constraints

Question asked by rigodiaz on Dec 13, 2017
Latest reply on Dec 14, 2017 by rejeesh

Hi Guys,

 

I noticed that going from 'hdl_2016_r2' to 'hdl_2017_r1' the reference clock constraints for rx_ref_clk and tx_ref_clk changed.

 

Here:

hdl/system_constr.xdc at hdl_2017_r1 · analogdevicesinc/hdl · GitHub 

 

Before:

set_property -dict {PACKAGE_PIN L8} [get_ports rx_ref_clk_p]
set_property -dict {PACKAGE_PIN L7} [get_ports rx_ref_clk_n]
set_property -dict {PACKAGE_PIN G8} [get_ports tx_ref_clk_p]
set_property -dict {PACKAGE_PIN G7} [get_ports tx_ref_clk_n]

 

After:

set_property LOC GTHE4_COMMON_X1Y1 [get_cells -hierarchical -filter {NAME =~ *i_ibufds_rx_ref_clk}]
set_property LOC GTHE4_COMMON_X1Y2 [get_cells -hierarchical -filter {NAME =~ *i_ibufds_tx_ref_clk}]

 

On the new contraints, how do you differentiate between MGTREFCLK0 or MGTREFCLK1? 

 

Much appreciated!

 

Thanks,

 

Rigo

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