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A question about the frequency resolution of DDS

Question asked by touch1995 on Dec 12, 2017
Latest reply on Dec 20, 2017 by touch1995

Hi, recently I try to use AD9833 to realize a BFSK signal, For example, FREQ0 is 1.001MHz and FREQ1 is 1MHz. In theory, when clock rate is 25MHz and the frequency registers are 28 bits wide, the delta phase M0 to FREQ0 is M0=10737418.24, the delta phase M1 to FREQ1 is M1=10748155.65. However, phase accumulator will both overflow after 25 clock cycles. How does the signal show the difference between two frequencies?