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SHARC SPI Boot failure (ADSP21363)

Question asked by davew on Nov 15, 2011
Latest reply on Nov 28, 2011 by Mitesh

Hi,

the SHARC manual states that TRST must be either tied low or pulsed low at power up in order for the device to boot successfully from SPI.  On a previous board design I used a jumper on the JTAG header to tie TRST down but our production and field support department (understandably) don't like this because it is potentially unreliable and means someone has to remove the jumper to enable JTAG testing and refit it in the correct position afterwards.  Also because the SHARC is in a JTAG chain with other devices on the board, the SHARC header is really surplus to requirements and they would rather not have to fit it.

 

On my latest design I added some logic to hold TRST down for approx 200mS after power up.  This does not seem to be reliable on all boards so I will have to revert to header and jumper solution.  I have found that performing a second SHARC reset and SPI boot always seems to be successful and I have never had any booting issues with TRST tied low as in the previous design.

 

The datasheet is a bit woolly on the TRST requirements - the only constraint on TRST seems to be that it has to be a minimum of 4 TCLK cycles wide but obviously when the board powers up in use, there is no TCLK.  Does anyone know what the real requirements for TRST are?  Does it really have to be tied permanently low to guarantee successful boot?

 

 

Regards,

Dave.

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