would it be possible to disable the VCO band selection in order to reduce the PLL lock time?
If you skip the auto-calibration, you will need to make sure you have selected the right band. Not selecting the right band can lead to a few issues:
Over temperature, the vtune voltage will shift to maintain lock. If the vtune voltage gets too close to the charge-pumps rails, then we can lose lock, or have poor phase-noise/spurious performance.
This is not really functionality we built-in intentionally. I am checking a way to disable the VCO auto-cal with a designer.
By the way, it takes less than 2.5ms to lock at the condition where specified in datasheet (refer to figure 36). What is your requirement in your application?
thanks for the answer. I simulated the PLL with ADIsimPLL.
With a 25 MHz PFD (fref = 50 MHz) and 20 kHz loop filter, the lock time is approximately 4 ms.
I need to perform small frequency step, max 1 MHz with a carrier of about 1 GHz.
My target lock time is < 1 ms.
I was wondering if it possible to enable the VCO band selection at the PLL start-up, perform the calibration and store the data so that to exploit them during the operating conditions.
I was not able to find a more accurate description of the VCO_CTL2 register.
Could you please explain how the fields VTUNE_CTRL and VCO_BAND_SRC work?
Below is the summary of the procedure for the fast lock time on ADRF6720. Basically, get/save the VCO Band information at beginning for the specific frequency. Skip auto-calibration and use this. Some register information( reg.0x44,reg. 0x46) are not in datasheet assuming a customer doesn't need to access these register. However, below procedure asks to read and write. Please refer to ADRF6820 datasheet for those registers that ADRF6720 shares.
I wish it works for your system.
Set the 0x02, 0x03 and 0x04 finally based on LO frequency;
2. Once the VCO is locked, read the LD at the Muxout Pin; if LD is high, then indicate the VCO is locked;
3. Read back register 0x46 bits <6:0> that is VCO_Band Readback via SPI, assume it is A; save the register value for frequencies on EEROM; so this may need to create a table as below;
4. To reduce the LD time, ADRF6720 can be working on the band selection manually; here is the programming procedure for this function;
a) Set 0x44 as 0x0001: Disable band cal algorithm;
b) Set bit7 as 1 for 0x45,
Set the band value to bits[6:0] in 0x45;
c) Select the appropriate VCO via 0x22 (bits 2:0); Refer to Table 6
fVCO or fEXT (MHz)
VCO_SEL (Register 0x22[2:0])
2850 to 3500
3500 to 4020
4020 to 4600
4600 to 5710
2855 to 3000
d) Update the register 0x02, 0x03 and 0x04;
e) Monitor LD to check if the frequency is locked;
Example: PFD=30.72M, LO=1600MHz;
Read band cal value. This is the band cal value for LO = 1600MHz.
Disable band cal algorithm
Bit 7 of Reg0x45 set to 1. This forces the VCO to use the band value programmed
Bits [6:0] program band value
Select the appropriate VCO
The above calibration procedure needs to be performed for each LO frequency to be used. It also needs to be performed for each ADRF6720 device, since the correct VCO band will change with process variation. The VCO band will not need to be updated for temperature variation.
Retrieving data ...