I am trying to connect AD9208-3000EBZ to a Xilinx FPGA board (VC108) following EVALUATING THE AD9208 / AD9689 ANALOG-TO-DIGITAL CONVERTER [Analog Devices Wiki] . After reading the mentioned webpage and the schematic of AD9208-3000EBZ (SCH_9689ce02c.pdf), I still have a some questions.
1. Is it necessary to generate the ADC sample clock (CLK+- of AD9208) and the FPGA reference clock (to clock the GTs) from the same clock source?
2. In Figure 5, J4 and J200 are Sysref+- and J202 is Ext Sysref to FPGA. From the schematic, the differential clock signals applied to J4 and J200 are connected to the SYSREF+- of AD9208. And the clock signal applied to J200 is used to generate a pair of differential clock signals (SYSREF_TO_FPGA+-) for the FPGA. Shouldn't the same SYSREF being applied to AD9208 and the JESD (rx) on the FPGA? Why is there an extra input for the SYSREF to the FPGA?
3. In Figure 5, J3 is Global Clock to FPGA. The clock signal applied to J3 is used to generate a pair of differential clock signals (GLBLCLK_TO_FPGA+-) for the FPGA. Will this clock be used on AD9208-3000EBZ or just passed to the FPGA? Is it necessary to generate this clock from the same clock source as the ADC sample clock?
Thank you very much.