Do you have a reference layout for the ADP5071 in SEPIC Mode on Ch1 and Inverter Output on Ch2, like shown on page 25 of the datasheet?
No reference layout since no EVAL board was done for a sepic configuration. But layout guidelines in page 26 should still apply. The layout screenshots on page 26 shows an example of the CH1 non-sepic and CH2 inverting regulator configuration.
Fil, thank you for your reply! Will consider and adapt the guidelines.
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