We have observed some misbehaviour on our adv7842 implementation that we need an urgent response to.
As a part of our manufacturing test we are running video loop test with various formats, such as 1920x1080p60 (148.5 MHz clock), 1920x1200p60 (pixelclock 154 MHz) and 1600x1200p60 (pixelclock 162 MHz).
During the testing we observed that there is either a duty-cycle shift, or a flipping of the LLC clock output.
This is the clock and V-sync at 153 MHz:
Increasing the pixelclock frequency to 154 MHz, the clock suddenly changes:
The signal runs to an FPGA which samples using the rising edge of LLC.
Hence the set-up time is somewhat derated when the clock flips.
Normally we ensure sifficient set-up and hold time for the FPGA by setting the phase of the internal DLL in the ADV7842. This is done using register 0x19.
However, above 154 MHz the phase adjustment does not work. We can invert the LLC clock, but any phase alignment register that works on 153 MHz pixelclock has no function above 154 MHz (up to at least 165 MHz). Hence we are not able to assign phase values making the deisgn work reliable towards the FPGA.
are there any explenations why the clock changes above 154 MHz?
And are there any explanations why the phase adjustemtn stops working when this happens?