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Unexpected change in SCLK on BF537 with VDK/LwIP

Question asked by MattZ on Dec 5, 2017
Latest reply on Apr 23, 2018 by MattZ

Hi All,


I have a custom board with a BF537 si 0.3. Upon boot up, a simple assembly boot loader is loaded off of sflash. The boot loader configures PPL, EBIU, etc. Then it loads the main program from sflash. Clock in is from a 25MHz crystal. MSEL=19, DF=0, BYPASS=0, SSEL=5, CSEL=0.


The relevant section of our boot loader is:

CLI R2; // Disable interrupts, copy IMASK to R2
P0.H = hi(SIC_IWR); // enable PLL Wakeup Interrupt
P0.L = lo(SIC_IWR);
R0 = [P0];
[P0] = R0;

P0.H = hi(PLL_DIV);
P0.L = lo(PLL_DIV);
R0 = 0x0005(Z); // SCLK = CCLK /5
W[P0] = R0;

P0.H = hi(PLL_CTL); // CCLK - CLKIN * 19, PLL Not Bypassed
P0.L = lo(PLL_CTL); // No Input or Output Delay Added,
R0 = 0x2600(Z); // All Internal Clocks on, CCLK on,
W[P0] = R0; // PLL Powered, Pass CLKIN to PLL
IDLE; // Drain pipeline, enter idled state, wait for PLL wakeup
STI R2; // After PLL wakeup occurs, restore interrupts and IMASK


The problem we are experiencing is periodically, after the bootloader loads the main program the program seems to be running way slower than expected and we measure SCLK with an o-scope to be about 1/3 less than expected. This happens frequently but not always. When the program runs as expected, we measure SCLK to be 95MHz (as expected). 


Does anyone have any ideas of how to figure out what is happening and how to resolve this issue?


Thanks in advance.