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Mathworks Hw/Sw co-design using ADI's BSP for multirate model

Question asked by rodrigo455 on Dec 5, 2017
Latest reply on Dec 5, 2017 by rodrigo455

Here's my problem:

"The custom IP always runs at the sample clock", but when modeling I have to specify a fixed sample time for a clock that will vary according to the sample rate. When I create a group of blocks that has a custom fixed sample time (different from sample rate), matlab create a relation between the clocks inside my IP given one single input clock (IPCORE_CLK), which is not desirable. The generated code gets all messed up. I would like to know if it's possible to generate a second input clock for the IP (a clock independent of IPCORE_CLK) to be used with this group of blocks. Will be required to edit the generated code?


thanks in advance.