I am working on a design that uses the ADV7181C to receive XGA video (1024x768 @ 60 Hz). The digitized data is being sent to an FPGA for processing using the 12-bit 4:4:4 DDR format. Looking at the timing information in the datasheet, at the XGA clock rate of 65 MHz t15 (clock rising to end of valid data) works out to be -0.15 ns. Does this imply that data is not guaranteed to be valid at the rising edge of the clock? Section 9.3 of the users manual states that register 0x89 contains a field (DDR_CLK_DEL) that allows the output clock delay to be adjusted but the description of register 0x89 does not mention these bits. Is it possible to adjust the DDR output timing?