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AD9152 SERDES PLL fREF

Question asked by zeahr on Dec 4, 2017
Latest reply on Jan 9, 2018 by jerryguo

Hi,

In the datasheet it is stated  "The reference clock to the SERDES PLL is always running at a
frequency, fREF, that is equal to 1/40 of the lane rate (PClockRate)."

 

I would like to know what is the source or where the fREF of SERDES PLL is connected from?

What is the relationship between SERDES PLL's fREF and DACCLK?

 

Thank you.

Best Regards,

Zeahr

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