AnsweredAssumed Answered

Change System Clock Frequency dynamically (on the fly) using bfrom_SysControl.

Question asked by BFProgrammer on Nov 14, 2011
Latest reply on Dec 22, 2011 by BFProgrammer

My program starts and I set CCLK=520MHz, SCLK=130MHz.

With these clocks I execute DMA transfer of 1.8MByte from NOR Flash to DDR.

In the second stage I have to transfer the received data from DDR to Altera FPGA through EPPI0 interface.

In order to achieve the most speedier result, i want to change the System Clock SCLK to something like 100MHz, because it will give me better opportunity to set the EPPI0 divizer,in order to get the greatest EPPI0 bandwidth, according to the following formula :

 

EPPIx_CLK = (SCLK) / (2 * (EPPIx_CLKDIV + 1)).

 

The problem is that using "bfrom_SysControl" dynamically, second time -  causes the DDR->EPPI0->FPGA transfer to fail. Without this

SCLK change the transfer succeeds.

Second time call of "bfrom_SysControl" with setting to CCLK=480MHz, SCLK=60MHz returns with error 0x00000701.

What does it means?

 

This failure contradicts to the explanation in chapter 18.Dynamic Power Management of BF54x Hardware Reference Manual.

Please help to understand the nature of the failure.

Peter.

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