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Questions about PLL design with HMC698LP5

Question asked by Se-woong on Nov 30, 2017
Latest reply on Dec 5, 2017 by MRichardson


My customer are designing PLL circuit  with HMC698LP5 (PLL), HMC391LP4(VCO) and OP27 (OPAMP).

And the ouput frequency are 3.9GHz or 4.05Ghz and the reference frequency is 50MHz.


Q1) when they implement a charge pump  of HMC698, can they implement up/down of charge pump at the same time?

Q2) At this time, can they implement a loop filter circuit as passive type?

Q3) They want to handle a fixed LO as 4.05GHz and 3.9GHz with one OP Amp. (OP27S).

       At this time, can they control a tune voltage with under 1V range through OP27S?


Q4)Would you check below their loop filter design?





Please advise me.