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ADuM6401 output state at VDD1 off

Question asked by Terumasa on Nov 29, 2017
Latest reply on Dec 18, 2017 by Terumasa

Hello

 

Please let me know your adivce for  output state of ADUM6401 at VDD1 off.

We think  that output becomes high-impedance throguh below 2 pattern  from the datasheet description.

Is it correct ?

 

1:   ADuM6401 holds last logic state

2:   output becomes high -impedance when VISO reaches UVLO

Or

1: ADuM6401 holds last logic state

2: output is set to default low  temporarily because there is not  input data pulse

3:  output becomes high -impedance when VISO reaches UVLO

 

Regards,

Terumasa

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