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AD9739 Clock Input Slew Rate Parameters

Question asked by jfs2412 on Nov 28, 2017
Latest reply on Dec 1, 2017 by saberbf


I am designing a circuit that drives the DACCLK input using the LVPECL standard. On page 40 of the datasheet it states that " The AD9739 clock receiver provides optimum jitter performance when driven by a fast slew rate originating from the LVPECL or CML output drivers."


Please can you quantify what 'fast slew rate' is, as it is not clear what the optimal range should be.