I want to know AD9162 JESD204B SYSREF Function.
There is a variation in the phase relationship between SYSREF and DACCLK when
JESD 204 B is operated in subclass 1. If it can not meet the setup hold time standard of
SYSREF described in datasheet 9 page, I think that the link of JESD204B will be broken.
Is there a status that alerts AD9162 that the link has expired or that it can not afford the setup hold time?
Or is there a function or setting that corrects the phase variation of SYSREF?
I would like to confirm these two things, please tell me about the following contents.
When I tried turning off the input of SYSREF when it operated without any problem,
the status of register 0x024 changed from 0x00 to 0x18.
Is it okay to recognize that bit 4 IRQ_SYSREF_JITTER on the datasheet page 84 will become '1'
unless it meets the SYSREF setup hold time standard?
Or, because there is no margin to the standard, will it be '1' when the phase adjustment of SYSREF
Also, at what point will IRQ_DATA_READY of bit 3 become '1'?
A description of SYSREF synchronization such as IRQ_SYSREF_JITTER is described
on page 54 and it is recommended to set SYSREF_JITTER_WINDOW of register 0x039 to
a minimum of 4 DAC CLK cycles, but what is this setting like?
For example, if you set 0x04 in the recommended 4DACCLK cycle, it can adjust the setup time
of SYSREF within the time of 4DACCLK cycles, so it will be enough for setup time, or at least
4 DACCLK cycles, SYSREF I think that it is either the necessity of Hi time from the rising edge
to the falling edge.
Please tell us about the following registers in relation to ② contents.
Registers 0x038, 0x37 SYSREF_PHASE 1, 0
Is it a status that can be used to adjust the phase on the data sending side (FPGA)
when using multiple DACs?
In that case, does it need it when using with a single DAC?
Or can it adjust the phase of received SYSREF?