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AXI_DMAC Data Ready Interrupt?

Question asked by rayking on Nov 27, 2017
Latest reply on Nov 27, 2017 by larsc

We are using a picozed SDR SOM2 board with LINUX  and designing our own FPGA. Right now, we are using the AXI DMA engine for the communication between FPGA and ARM CPU. For the DMA RX part, we only see two types of interrupts one for transaction pending and one for transaction complete. According to this Q&A https://ez.analog.com/message/324038-re-axidmac-how-to-configure-adcdma-trigger-interrupt-on-recieveing-data-block?comme… , Larx explained that the interrupt fires once all data has been captured. From what we observed, the transaction complete interrupt is for that purpose. But that requires ARM CPU to specify a data length before the actual communication. What if the ARM CPU does not know the data length before issuing the DMA transaction, but instead, waits for a data ready interrupt? Once the data ready interrupt is fired, ARM CPU then sends the RX transaction (with length specified) to the AXI DMA engine. We already implemented the FPGA part to inform ARM CPU about the data length. Can we piggyback the AXI_DMAC's interrupt for the data ready interrupt?

 

Thanks!

 

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