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AD9152 How to set CLK_SEL to select clock input from DACCLK+/-

Question asked by katsu on Nov 21, 2017
Latest reply on Nov 30, 2017 by katsu

Hello,

 

Q1. How to set CLK_SEL to select clock input from DACCLK+/-?
In our use case, DAC PLL is not used. So DAC PLL is disabled (0x083 bit 4 = 0). External clock generated by AD9528 is inputted to DACLK+/- port. I couldn't find DAC_SEL setting register in AD9152 datasheet.

 

Q2. Setting of DAC PLL unused case
Except DAC PLL related register setting, is initial setting between DAC PLL used and unused same? In case that the initial setting is different, please explain.

 

Best Regards,

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