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Multiple ADRF6720 output synchronization

Question asked by PieroS. on Nov 21, 2017
Latest reply on Nov 30, 2017 by PieroS.

Dear All

I have a board with 5 ADRF6720; the first is the master and generate the LOCAL signal (2x580MHz) and the other are slaves with the local passthrough as explained in the datasheet.

The clock supplied at each SSB are 28.6MHz and arrive to each with the same phase (PCB trace with same lenght). I want to output 433.92MHz Then I generate I and Q signal at the DDS at 146.08 MHz.

The I and Q signal for each ADRF6720 are perfectly in phase at DDSs outputs (between the 5 channel) but the RF output (after SSB) are not all in phase. Every each power-up they have randomly 0 degree or 180 degree each other.

I don't use polyphase and also I use 2x local distribution to avoid the 180° phase ambiguity as explained in the datasheet at page 20.

These are my configurations:

        --------------------- MASTER (generate LO) ---------------------------------

        0x0000,    //SOFT_RESET           {0}
        0xF77F,    //ENABLES                 {1}
        0x00A2,    //INT_DIV                    {2}  
        0x0352,    //FRAC_DIV                {3} 
        0x0DF7,    //MOD_DIV                 {4}  
        0xF000,    //ENBL_MASK            {5}
        0x0C26,    //CP_CTL                   {6}
        0x000A,    //PFD_CTL                 {7}
        0x0018,    //VCO_CTL                 {8}  
        0x00FF,    //BALUN_CTL               {9}
        0x1101,    //MOD_LIN_CTL          {10}
        0x0900,    //MOD_CTL0             {11}
        0x0020,    //MOD_CTL1             {12}
        0x0010,    //PFD_CP_CTL        {13}
        0x000E,    //DITH_CTL1            {14}
        0x0000,    //DITH_CTL2            {15}
        0x0000,    //VCO_CTL2             {16}
        0x14B0     //VCO_CTL3             {17}


        --------------------- SLAVES (are 4 slaves) ---------------------------------

        0x0000,    //SOFT_RESET     {0}
        0xF751,    //ENABLES           {1}
        0x0000,    //INT_DIV              {2}
        0x0000,    //FRAC_DIV          {3}
        0x0000,    //MOD_DIV           {4}
        0xF000,    //ENBL_MASK      {5}
        0x0C26,    //CP_CTL            {6}
        0x002A,    //PFD_CTL           {7}
        0x0004,    //VCO_CTL           {8} 
        0x00FF,    //BALUN_CTL         {9}
        0x1101,    //MOD_LIN_CTL    {10}
        0x0900,    //MOD_CTL0          {11}
        0x0000,    //MOD_CTL1          {12}
        0x0010,    //PFD_CP_CTL     {13}
        0x000E,    //DITH_CTL1         {14}
        0x0000,    //DITH_CTL2         {15}
        0x0000,    //VCO_CTL2          {16}
        0x14B0     //VCO_CTL3          {17}


any suggestion?