We use FMCOMMS3/4 with Zedboard/ZC706 kit in our application.
AD9361 is configured in Fast attack AGC mode. The receive input is a carrier signal. To test this mode, the receive input to AD9361 is turned on, signal power is varied and is turned off for some time (similar to that of a burst mode signal). In the FPGA, a debug ILA core with ADC inputs are added for monitoring the received ADC counts. The following are observed while using Fast AGC mode:
- While reading receive gain parameters, sometimes we could see the message “Failed to read gain, state m/c at state number x”
- ADC output level (observed as ADC counts) is not maintaining constant in Fast Attack mode while changing input power level. In Slow attack we could see that the Rx gain changes and maintains a constant ADC output level with variation in input signal.
- If the input signal is removed, we expect the AGC state machine to detect signal loss and state machine to return to state 1 from state 5. In our case we observed that state machine hangs and gain lock algorithm is not restarting unless we reboot the board.
Kindly provide your valuable suggestions to enable use of Fast AGC.