I am unclear of the DMA operation of SPORT0 and SPORT1 when used simulatneously in the ADSP-21062.
I have SPORT0 transmitting words (internal memory -> SPORT0) and SPORT1 receiving words (SPORT1 -> internal memory). They both work on the internal clock. Transmission on SPORT0 is done to an internal SFRAME and reception on SPORT1 is to an external SFRAME.
Could you confirm that when both these DMA channels are active at the same time, where there will be any complications?
Theya re both accessing the internal memory, but of course not the same address.
The documentation doesn't give a proper explanation to this situation. According to the manual:
"The DMA controller determines the highest priority requesting channel during every cycle, between each individual data transfer."
In this case SPORT1 receive has the highest priority and could this interfere with SPORT0 transmission?