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AD9681 - FPGA data transfer problem

Question asked by Art55555 on Nov 17, 2017
Latest reply on Nov 30, 2017 by DougI

Hi!

I have AD9681 and Artix7.

Now, I use:

CLK_PIN- IBUFDS-IDELAYE2-ISERDESE2.

DATA_PIN- IBUFDS-ISERDESE2.

 

DDR two-lane, bytewise.

Delay (for clk) and bitslip operation are doing manual (by VIO)

clk-line (after ISERDESE2 ) alwsys indicates "AA"

fco-line (after ISERDESE2 )  indicates "F0" after bitslip operation.

If ADC if going test (0D register - 04,09) - correct data (after bitslip).

But signal is bad!

 

I used XAPP524, XAPP585.

 

 

 

 

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