I have AD9681 and Artix7.
Now, I use:
DDR two-lane, bytewise.
Delay (for clk) and bitslip operation are doing manual (by VIO)
clk-line (after ISERDESE2 ) alwsys indicates "AA"
fco-line (after ISERDESE2 ) indicates "F0" after bitslip operation.
If ADC if going test (0D register - 04,09) - correct data (after bitslip).
But signal is bad!
I used XAPP524, XAPP585.