I am using the axi_i2s_adi (dev branch) IP block in a Zynq+ Vivado 2017.2 design targeted for P/N xczu2eg-sbva484-1L-i and it is failing timing. See below. Can you help?
Paths failing timing.
Active Constraints for the I2S IP block
AXI_I2S IP Configuration
Schematic showing one of the data paths that is failing.