Could you state INTRQ1/2/3 pin condition of the ADV748x when it set to power down, output L or Hi-Z
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If you check the hardware manual ADV748x_HardwareManual_RevPrB_2014-07-11.pdf at page no of 17, you can see that in power down mode, when master_pdn or core_pdn are set to 1, all the blocks are powered down except the I2C slave, CEC and the interrupt generator. So it depends on how you have configured the INTRQ pins. By default, INTRQ2 and INTRQ3 are powered down, so High-Z. By default INTRQ1 is powered up, but is set to open drain, so High-Z (but it can drive low if a CEC wake up event happens).
Thanks, I've missed the point.
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