My team noticed that a received signal phase noise is getting stronger when the external reference clock frequency is lower.
This is also stated in UG-570: "For optimum phase noise it is recommended to operate the scaled clock as close to 80 MHz as possible." (p. 15)
My question is why is this behavior occurs? And also, could it be possible to bypass it so we can get optimum phase noise performance while using lower external reference clock frequencies?
Thank you in advance,