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AD9144 in 8-lane configuration

Question asked by rigodiaz on Nov 13, 2017
Latest reply on Nov 14, 2017 by rigodiaz

Hi Everyone,


I'm trying to use the AD9144 chip with eight lanes on a custom board that based off of the DAQ2 design.


I've doubled everything up in the HDL. I have a user-space driver based from the no-OS version. So far I've expanded the "ad9144_channels" struct array to four channels, this gets passed into dac_data_setup(). In ad9144_setup(), I have modified the transport layer section to match "JESD204B Mode 0" in page 51 of the data sheet.


I have not modified the jesd and xcvr drivers or their inputs.


I'm using the tone generation feature (DAC_SRC_DDS) to test the ouputs. I get a short-pattern-test mismatch for every lane when I run the driver. But, surprisingly I still get a tone out of TX1 (channels 1 and 2) and nothing out of TX2 (channels 3 and 4). All of the registers checked in ad9144_status() are 0xFF which should be a good sign for 8 lanes.


I've looked through the util_daq2_xcvr source and the configurations for the rest of the IP cores and I feel pretty good about how I configured those.


Is there something I might be missing in the driver? And, probably a long shot, is there any reference code for an eight lane setup?


Any help is appreciated.







I missed TXEN1 so now TX2 works. However, I'm not getting the right tones. Right now channel 3 is the same tone as channel 1 and channel 4 has the same tone as channel 2. In other words TX2 is mirroring TX1.