since four years we used the ADRF6602 as a down-converter. LO freq. = 1605,425MHz. We never changed the hardware (PCB) and also the software was never changed. The converter worked fine the hole time. Now - arround four years later a problem appears: arround 40% of the used chips can't lock the PLL after init the register. Here are some hints related to this design:
# Ref. is a 40.0MHz Oscillator / The level at the ADRF6602 is arround 100mVss + Bias DC ( I also changed this level up to 1Vss - no changes)
# I used the tool "Analog Devices ADRF6x0x Customer Evaluation Software v6.1.0" to configure all registers. The output of this tool (Hex dump) is used by a little controller to program the ADRF via SPI. Here is the output :
REG0: 00 01 40
REG1: 00 32 01
REG2: 00 06 CA
REG3: 70 00 0B
REG4: 0A A7 A4
REG5: 00 00 6D
REG6: 1E DD 8E
REG7: 00 00 07
# the programming order is (as discriped in your datasheet):
0) after power up: delay 1second before start init
1) write to REG5: PLL disabled
2) delay (150ms to 500ms used - no changes )
3) REG5: PLL enabled (delay 100us)
4) REG7 (delay 100us)
5) REG6 (delay 100us)
6) REG4 (delay 100us)
7) REG3 (delay 100us)
8) REG2 (delay 100us / up to 200ms tested)
9) REG1 (delay 100us / up to 200ms tested)
10) delay (150ms to 500ms used - no changes )
11 ) REG0 (init finished)
12) delay (150ms to 500ms used - no changes ) .. for VCO recalibration
13) check "lock detect"
# A downconverter which works showed:
- a "Vtune" voltage of 2.002V (f out = 1605,41914 MHz)
- A power consumption @5V (total, include 2 pre-amplifer and a micorocontroller) 244mA before / 268mA after init
- Vtune at scope looks like figure22 in your datasheet (LO freq. vs. lock time)
MUX out (lock detect) = stable 'high'
# A downconverter which doesn't works showed:
- a "Vtune" voltage of 3.046V (f out = 1634,754 MHz) (not stable) (Example!)
- A power consumption @5V (total, include 2 pre-amplifer and micorocontroller) 230mA before / 255mA after init
- MUX out (lock detect) : a 'low' and mostly a short "high" every 100us. This is the same time as seen as Vtune ramp-up time. Which means that the Vtune voltage rises from 0V to >3V in arround 100us.
# I shorted the Vtune voltage to see what the max. VCO range is. All boards produce a broad frequence range much MHz below and above the needed LO-frequency.
# I switched the "VCO Band Select ans SW Source" from "Band cal" to SPI and offer different values to the "Band select".
I found that the value decimal "49" was closed to the needed frequency - but also in this case the chip doesn't 'lock'.
# Here are some samples (LO frequency) - produced by the same hardware and software (programmed: 1605,425MHz):
1885,0 | 2265,0 | 1185,0 | 2267,5 | 1185,0 | 2252,5 | 2267,5 | 1622,5 MHz
At some boards I can't see a LO signal in the range of 1GHz to 4GHz ( LO output driver = always enabled ).
SPI signals: the SPI clock frequency is about 2MHz, delay from LE =low to first clock is arround 1.2 to 1.3 us.
LE idle = 'high' / clock idle = 'low' / data: MSB first
OK - are there any changes by the used ADRF6602 chips? Are there any helpful hints for me?