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AD7124 input current nonlinearity in buffered mode

Question asked by KDV on Nov 13, 2017
Latest reply on Nov 20, 2017 by JellenieR

Hello! During testing of the evaluation kit EVAL-AD7124, I've been found that input currents of the buffered analog inputs has strong nonlinear behaviour that depends from the common mode voltage at the buffered analog inputs.

 

Test setup was as follows:

 

  1. Schematic (part of the evaluation kit schematic EVAL-AD712)

    AIN0 / AIN1 analog inputs was used for evaluation as shown on the figure below:
    Legend:
     - Components with red cross has been removed
     - "Red" resistor is 1Meg. This resistor was mounted close to the analog inputs AIN0 / AIN1

  2. Test plan
     - Ambient temperature: 25...27C
     - R34 connected to the external low-noise, low impedance, programmable voltage source (CA100 YAKOGAWA). This external source provides programmable common-mode voltage for the AIN0 / AIN1 pair
     -  Step 0. Set common-mode voltage at the AIN0 /  AIN1 to the predefined value by programming CA100
     -  Step 1. AD7124 measures single ended AIN0 / GND voltage that is equal to the voltage from external source (CA100). Detailed configuration can be seen in the figure below - refer to "Channel 0" 
     -  Step 2. AD7124 measures its zero offset (refer to "Channel 1") by connecting both AINP and AINM to the AIN0. Used to eliminate CMRR effects. But in fact, CMRR effect was negligible in all configurations. 
     -  Step 3. Measuring AINP input current: AD7124 measures AIN1 / AIN0 differential voltage. AINP connected internally  to the AIN1 and AINM connected internally to the AIN0. This voltage equals to the AINP input current multiplied by 1Meg resistor. Thus we have AINP current (refer to "Channel 2" at the figure below)
     - Step 4. Measuring AINM input current: same as Step 3, but now AINP and AINM has been reversed to measure the AINM input current (refer to "Channel 3" at the figure below)
     - Repeat Step0 ... Step 4 for gains 2..128 

    Configuration of the channels:



    Configuration of the Gain / Buffers (example shown for Gain = 128):



    Configuration of the references: 




  3. Results

    Gain = 128:

    Notice the rapid change in the input currents while crossing AVDD/2 

    Gain = 64:

    Almost the same behavior as for the GAIN = 128, but slightly shifted down by 0.7nA. The same rapid changes while crossing the AVDD/2 

    GAIN = 32:

    Again, the same behavior as for GAIN = 128 and GAIN = 64. Shifted down by 1.6nA compared with GAIN = 64

    GAIN = 16:

    GAIN = 8:

    For GAIN = 8, rapid changes in the input currents while crossing the AVDD/2 still exists, but it is noticeably lower compared with GAIN = 128...16. I guess that could be explained somehow by the fact that only single PGA stage is active in the AD7124 for GAIN = 2...8 (according to Figure 78 in the datasheet), while for GAIN = 128...16 both PGA stages are active 

    GAIN = 4:

    GAIN = 2:


    Obviously, such an rapid changes in input currents of the buffered analog inputs might dramatically reduce accuracy of the measurements, especially for external sensors that are biased around the AVDD/2 and have significant impedance (sach as bridge sensors or RTD). Moreover, any externally induced noise capable to change common-mode voltage of the sensor will significally affect resulting accuracy by modulating the input currents of the ADC. This impact might be interpreted as poor CMRR, but actually it has different nature (CMRR has almost no effect)

  4. Questions

    1. Can AD admit the desribed above effect ? If no, what setups /  measurements were wrong ?
    2. Is it possible, in order to minimize effect, to use only half of the common-mode range (up to the point AVDD/2, but not crossing it for sure)?
    3. Can AD assure that common-mode region up to the AVDD/2 is free from desribed rapid changes of the input currents ?

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