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Fmcdaq2 adc/dac sampling control

Question asked by cerasic on Nov 13, 2017
Latest reply on Nov 20, 2017 by andrei_g

Hi Istvan, Rejeesh and Lars,

 

First of all, I want to mention you that our  system based on fmcdaq2 hdl (R2017_R1 and No-OS dev branch from August 2017, is working even if it is not stable, it works in one configuration ADC (300 MSPS) and DAC (300 MSPS).

I have  checked  FMCDAQ2 without our design, all possible sampling frequencies for DAC and ADC. 

When I say it works, that means I capture the right data in the memory, I don't worry about the PN sequences or automatic tests.

I capture good data Each  time I get the following Uart message :

         2 - ADC  500 MSPS; DAC 1000 MSPS
          jesd_status jesd_status: out of sync (4)!
            jesd_status jesd_status: not in data phase (4)!
            adc_setup adc core initialized (500 MHz).
           dac_setup dac core initialized (1000 MHz).
           main ad9680 - PN9 sequence mismatch!
            main ad9680 - PN23 sequence mismatch!
            daq2: transmit data from memory
            daq2: RX capture done.

Only when I use configuration 8, I capture NO data  and I get the following Uart message :

         8 - ADC  300 MSPS; DAC 600 MSPS
         xcvr_setup ERROR: XCVR initialization failed!
          jesd_status jesd_status: out of sync (1)!
          jesd_status jesd_status: not in data phase (1)!
          jesd_status jesd_status: out of sync (4)!
          jesd_status jesd_status: not in data phase (4)!
           adc_setup adc core initialized (300 MHz).
           dac_setup dac core initialized (600 MHz).
           ad9144_status : CGS NOT received (0)!.
           ad9144_status : ILAS NOT received (0)!.
           ad9144_status     : framer OUT OF SYNC (0)!.
           ad9144_status : check-sum MISMATCH (0)!.
           ad9144_short_pattern_te    st : short-pattern-test mismatch (0x0, 0x0 0xA1A0, 0x0)!.
           ad9144_short_pattern_test : short    -pattern-test mismatch (0x0, 0x1 0xB1B0, 0x0)!.
            .................................
           ad9144_datapa    th_prbs_test : PRBS OUT OF SYNC (1)!.
           ad9144_datapath_prbs_test : PRBS I channel ERRORS (FF    )!.
           ad9144_datapath_prbs_test : PRBS Q channel ERRORS (FF)!.
           ad9144_datapath_prbs_test : PRB    S OUT OF SYNC (5)!.
           ad9144_datapath_prbs_test : PRBS I channel ERRORS (FF)!.
           ad9144_datapath    _prbs_test : PRBS Q channel ERRORS (FF)!.
            main ad9680 - PN9 sequence mismatch!
            main ad9680 - PN23 sequence mismatch!
            daq2: transmit data from memory
            daq2: RX capture done.

HERE ARE ALL COMBINATION I HAVE TESTED  :
ad_printf ("\t1 - ADC 1000 MSPS; DAC 1000 MSPS\n");
ad_printf ("\t2 - ADC 500 MSPS; DAC 1000 MSPS\n");
ad_printf ("\t3 - ADC 500 MSPS; DAC 500 MSPS\n");
ad_printf ("\t4 - ADC 750 MSPS; DAC 750 MSPS\n");
ad_printf ("\t5 - ADC 600 MSPS; DAC 600 MSPS\n");
ad_printf ("\t6 - ADC 375 MSPS; DAC 375 MSPS\n");
ad_printf ("\t7 - ADC 300 MSPS; DAC 300 MSPS\n");
ad_printf ("\t8 - ADC 300 MSPS; DAC 600 MSPS\n");
ad_printf ("choose an option [default 1]:\n");

  ALL OFF THEM GAVE GOOD DATA      except number 8)    ADC 300 MSPS; DAC 600 MSPS

for my understanding 8) ADC 300 MSPS; DAC 600 MSPS is  similar to number  2) ADC 500 MSPS; DAC 1000 MSPS

when I change pll2_vco_diff_m1 = 5; instead of 3    and adapt the lane_rates and the ref_clocks.

 

PLEASE can check the configuration Number 8 in the attached fmcdaq2_reconfig.c routine.

 thanks for your support,

     Best Regards M. Daoudi

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