I'm looking for some clarification on which LVDS pins or the AD9361 have an onchip termination option.
The data sheet says all Rx and Tx data pairs (Table 13 - every description of TX_Dx_p/n and RX_Dx_p/n ... no other signals)
The register definitions (0x03c, D5) refers to the setting as "Rx On Chip Term" and say all data path bits plus TX_FRAME and FB_CLK.
I don't see why the termination would be on the Rx path and if it were why the RX_FRAME and DATACLK would be excluded. Including the two other LVDS inputs (TX_FRAME and FB_CLK) in the register definition suggests the LVDS inputs have the termination option. But ... we can't design on what we imply or assume.
Can we get some clarification and how do we file a doc enhancement request?