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AD9364 LVDS moudel DATA_CLK

Question asked by 华电小哥 on Nov 11, 2017
Latest reply on Nov 13, 2017 by sripad

Hello.
I am using AD9364 LVDS mode RX, currently encountered a problem, according to technical manual, the maximum rate of DATA_CLK when using LVDS mode can reach 245.76M, but I found that in actual use when I set the DATA_CLK frequency is higher than 61.44M and less than 220M, DATA_CLK will have a larger phase noise and clock will have a large deformation, when I set the DATA_CLK frequency is higher than 220M phase noise will return to normal. However, the phase noise of CLK_OUT is acceptable when it is less than 245.76M. Because what registers are not set correctly, or because of what calibration errors?
Look forward to your reply

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