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axi_ad9361_dac_fifo in zedboard+fmcomms4

Question asked by IPrium on Nov 6, 2017
Latest reply on Nov 7, 2017 by CsomI



I'm trying to send continuous stream to DAC with libiio (Zed+FMCOMMS4) and hdl_2016_r2 branch.

I connect ILA to axi_ad9361_dac_fifo inputs and outputs and use simple 8-bit counter as data stream.

With ILA I see correct counter at axi_ad9361_dac_fifo inputs but not at outputs. I see that axi_ad9361_dac_fifo reacts only on 1 of 8 dac_valid pulses and outputs counter only once at 8 cycles. Counter sequence at output ports goes 8 time decimated.

Input (8-bit counter in two 16-bit input ports):


Ouput (decimated by 8 counter, error?):


Also, I see that dac_fifo_din_valid signal doesn't aligned correctly with dac_fifo_din_data and active only in pauses. Maybe it's reason why fifo outputs wrong counter? "FIFO write" works in wrong moment and saves 8 times same counter value in pause.


Danil Shendrik, IPrium LLC