The trigger mechanism for an oscilloscope is different from what IIO offers, at least how I understand it. While IIO uses the trigger to transfer each sample separately, an oscilloscope (or logic analyzer) uses the trigger to stop a stream of data after a set number of samples (post trigger time).
Let me explain a common case. After pressing the RUN button on an oscilloscope, the input stream is being written into a ring buffer (you might call it a FIFO, the behavior is the same). After the buffer is full old data gets overwritten (buffer SIZE). The same buffer can be overwritten many times before a trigger arrives. The trigger activates a sample counter. After the counter is exhausted (CNT samples) writing into the buffer stops. The last write pointer (PTR) can be anywhere inside the buffer. In a general case the buffer then contains (SIZE-CNT) samples before the trigger and (CNT) samples after the trigger. It is possible the trigger arrived before (SIZE-CNT) samples are written, but this is not important for this question.
An application would like to display the entire SIZE of the buffer. For a normal ring buffer the reading would start at PTR+1 continue till the end of the buffer (SIZE-PTR samples), wrap to the beginning and read the rest (PTR samples).
This can be achieved as described with two read loops or a single loop where modulo SIZE is used to calculate the address.
The above process for reading the buffer can only be used if the application is aware a ring buffer is used, it does not allow third party applications to use the buffer transparently. In other words you can not simply pass a pointer to an application, instead data has to be copied to another location first. We all know, copying is not desired.
A solution is to use the "magic ring buffer" (I could not find the best description, but most links Google finds reference the same concept). The basic principle is to map the physical memory containing the buffer data twice continuously into the virtual memory. I have done this in HW by mapping a buffer inside FPGA twice (partial address decoding). The process can be done using a MMU in user space and kernel space, but I did not try it yet. It is not as simple as is could be.
The advantage is obvious, PTR can be passed directly to a third party application, and there is no need for it to know where the buffer wraps, since the second buffer mapping continues where the first mapping ends.
The questions are:
- How does the concept of an oscilloscope trigger translates to IIO kernel drivers and LibIIO? If it does not, what would have to be changed/added?
- Would be possible to add "magic ring buffer" support to LibIIO?
NOTE: I only had Xilinx ZYNQ XADC to IIO driver to play with, and its buffer support is buggy.