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ADSP-21261: FLG0 input in SPI master boot mode?

Question asked by rolf on Nov 8, 2011
Latest reply on Nov 8, 2011 by rolf

Hi there,

 

I am having the following problem on an ADSP-21261. My goal is to use FLG0 as input (for a dip switch), using the parallel port pins as FLGs (FLG0-15 on AD0-15). So I set PPFLGS on SYSCTL and clear FLG0O on FLAGS during init, right? So far so good. When I simulate in ViusalDSP (using Simulator or attached via HPUSB-ICE), this works fine, the dipswitch is read as expected from pin AD15. However when I boot the DSP from my SPI flash in master boot mode (BOOT_CFG1-0: 01) the FLG0 doesn't seem to read its input correctly (always 0 on input). When I refer to another dipswitch on another FLG (e.g. FLG1), the input is read correctly. Could it be that due to the use of FLG0 during SPI master boot, the internal input pullup for FLG0 is disconnected somehow? Or is FLG0 hardwired as output in SPI master boot mode? Could anyone please try to reproduce this? Any workaround available?

 

Best regards,

 

Rolf Anderegg

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