I am using AD9364 and Custom ASIC for my application, configuration of AD9364 is done and I am able to see the LO leakage on Tx side. I have set TX LO to 2.4GHz and RX LO to 2.0GHz. Design includes AD9364 interfaced to ASIC through Level translator in CMOS mode. TX_FRAME and RX_FRAME clocks for samplling is getting generated. My queries are,
- I could able to see the data ( P0_D0/TX_D0---)on TX_data pins (In design Double data rate is implemented). But, on RX path, ( P1_D0/RX_D0 --)I am not able to see any data activity on RX_data pins. what might be reason to face this in FDD mode?
- Once I successfully program AD9364, I set the LO,sampling frequency and bandwidth using API function for both RX and TX. I can able to see the LO Leakage at O/P RF port only after I power ON it then I see the LO leakage for some seconds, then It dissappears. Is this normal case? Why it's not showing continously on Spectrum analyzer? Am I missing any more configuration? Is there any other functions to be called from API? Anticipating your help on this, - Regards, Aaryan