AnsweredAssumed Answered

The output of the AD9467 is LVDS level standard, now,my FPGA corresponding  BANK is powered by 1.8V. Is it  feasible?

Question asked by kuailelinghun on Nov 2, 2017
Latest reply on Nov 3, 2017 by UmeshJ

The output of the AD9467 is LVDS level standard, now,my FPGA corresponding  BANK is powered by 1.8V, Is it  feasible? I've read ADI's UCF file on the evaluation board of AD9467, the FPGA pins is constrained to "LVDS_25". But now, my FPGA BANK is powered by 1.8V, I want to know :

if my FPGA pins is constrained to "LVDS" , It's feasible?

Outcomes