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Using AD9361 reference design in custom project

Question asked by RafciuK on Nov 2, 2017
Latest reply on Nov 2, 2017 by rejeesh

Hi,

I have developed my own IP cores implementing base band processing (TX and RX) for wireless transmission of a 6Mbit/s stream of data. On TX side the IP core produces on the output several samples per input bit due to coding, pilot symbol insertion, up-sampling, etc. Now I'm trying to put the IP core inside the AD9361 reference design and reuse as much from the design and libiio as possible to communicate (transfer bits) with the PS on the PicoZed SDR board. However, from what I have read so far searching through all the posts and wiki pages, my IP core should be able to produce 1 output sample per 1 input sample every clock cycle. What changes should be made to the original reference design and/or libiio to overcome the limitations and enable different sampling frequencies at the input and the output of my IP core? Any suggestions are welcome :-)

 

Rafal Krenz

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